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IIT Delhi has been conducted GATE exam for Electrical Engineering (EE) on 8 February 2020 in the morning session. After successful completion of the exam candidates are looking for the answer key and paper analysis for reviewing their answer with the answer sheet and want to get a rough idea about their performance and how much marks they will get in their entrance exam. In the paper analysis, candidates will get the type of questions asked and the number of question asked, the pattern of the question and difficulty level of the questions papers. In this article, you will get complete information about GATE EE Paper Analysis 2020.
GATE EE Paper Analysis 2020
- The exam was conducted from 9:30 am to 12:30 pm
- The difficulty level of the exam was moderate.
- Power System carried 13 marks
- 24 questions were numerically based
- Questions from Analog Electronics were the toughest.
- Electrical Machines and Signals & Systems had a weightage of 13% and 11% respectively.
2019
GATE EE Paper Analysis by Gate Academy
| S.No. | Topics | Percentage wise weightage |
| 1 | General Aptitude | 15% |
| 2 | Engineering Mathematics | 10% |
| 3 | Network Theory | 8% |
| 4 | Signals & Systems | 6% |
| 5 | Control Systems | 8% |
| 6 | Analog Circuits | 8% |
| 7 | Digital Circuits | 7% |
| 8 | Measurement | 4% |
| 9 | Power Electronics | 10% |
| 10 | Electromagnetic Theory | 2% |
| 11 | Electrical Machines | 12% |
| 12 | Power Systems | 10% |
Detailed GATE EE Paper Analysis by Gate Academy
| Subject Topics | No. Of Questions | Topics – Questions were asked from | Difficulty Level | Total Marks |
| Engineering
Mathematics |
1 marks- 2
2 marks- 4 |
Newton Raphson, Probability, Calculus,
Matrix, differentially equation, Laplace transform, |
Tough | 10 |
| Network Theory | 1 marks- 2
2 marks- 3 |
Transient Analysis, Steady State Analysis, Two Port Networks, Basics of networks | Medium | 8 |
| Signals & Systems | 1 marks -2
2 marks- 2 |
Sampling, Filter, System analysis, Linear Time Invariant(LTI) Systems | Tough | 6 |
| Control Systems | 1 marks -4
2 marks- 2 |
Basics of Control System , Nyquist plot, Root locus, Bode-plot, Stability & Routh Hurwitz Criterion | Tough | 8 |
| Analog Circuits | 1 marks- 4
2 marks- 2 |
FET amplifier, BJT Amplifier, Op-amp, Diode Circuits-Analysis and Application, Transistors | Easy | 8 |
| Digital Circuits | 1 marks- 1
2 marks- 3 |
Logic Gates, Counters, Excitation machine, Kmap, Boolean Algebra | Easy | 7 |
| Measurement | 1 marks- 2
2 marks- 1 |
Power Factor Measurement, Energy Meter | Medium | 4 |
| Power Electronics | 1 marks- 2
2 marks- 4 |
Basics of Power Semiconductor Devices, Input power factor, Chopper, Convertor, Inverters | Tough | 10 |
| Electromagnetic
Theory |
1 marks- 2
2 marks- 3 |
Electromagnetic Field | Medium | 2 |
| Electrical Machines | 1 marks- 2
2 marks- 5 |
DC Machine, Transformer Losses, Induction Machine, Synchronous Machine, Special Machines | Easy | 12 |
| Power Systems | 1 marks- 2
2 marks- 4 |
Transmission Line, Economics of Power Generation, Fault analysis, Power Factor | Tough | 10 |
| General Aptitude | 1 marks- 5
2 marks- 5 |
Distance time, Probability, Permutation and Combination | Medium | 15 |
| Total | 65 | 100 | ||
GATE EE Cut off
Cut off is the minimum marks required to qualify for the examination by which candidates will get admission in the IITs for M.E/M.tech or PhD (Doctorate in Philosophy). Candidates whose marks will not meet the minimum cut off marks, not eligible for admission in the top engineering colleges. Here we are listed last 5 year cut off trends:
GATE Qualifying Cut off for EE (2013-2017)
| Year | General | OBC | SC/ ST/ PH |
| 2017 | 25.20 | 25.20 | 16.70 |
| 2016 | 25.1 | 22.5 | 16.7 |
| 2015 | 25 | 22.5 | 16.67 |
| 2014 | 25 | 22.5 | 16.67 |
| 2013 | 25.74 | 23.17 | 17.16 |
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